(1) Field of the Invention
The invention relates to a method of making complementary metaloxide-semiconductor field effect transistors (CMOSFET) and more particularly to a process of forming dual-gate structure by using only three masking steps.
(2) Description of the Prior Art
As semiconductor devices continually progress towards denser packing of active devices, the dissipation of the heat generated by the active devices in an integrated circuit becomes an extremely important issue. Under the consideration of power consumption and digital circuit application, the voltage operated CMOS transistors which have very high input impedance, are tolerant of large variations in supply voltage, consume almost no power in static condition and result in very good noise margins in digital circuit have become the most extensively used devices in modem Very Large Scale Integrated Circuit (VLSI) or Ultra Large Scale Integrated Circuit (ULSI). There are numerous known methods of making CMOS transistors. But most of them need at least five masking steps to have only one type of gate material formed on both of PMOSFET and NMOSFET.
FIG. 1A through ID illustrate a typical CMOSFET fabricating process using five masking steps to form the N type poly-silicon gate on both PMOSFET and NMOSFET.
First, as shown in FIG. 1A, a N well region 200 is formed into a P type silicon wafer 100 using conventional process steps, known to one skilled in the art. Thereafter, local oxidation region (LOCOS) 300 is grown to define PMOS and NMOS region on the wafer 100. Subsequently, conformal layers of gate oxide 101 and N type poly-silicon 120 are formed overall and then patterned to form the gate structure with the aid of the first masking of photo resist 400.
Referring now to FIG. 1B, a second patterned masking of photo resist 400 is formed over the PMOS region. The photo resist 400 formed over the PMOS region acts as the protection layer of PMOS region when NMOS region is subjected to ion implantation. Subsequently, the wafer is subjected to N type ion implantation 410 to form lightly doped regions 411 of NMOS. Thereafter, the photo resist 400 is removed from the wafer to avoid the contamination of photo resist in the followed deposition process.
Referring now to FIG. 1C, a conformal layer of oxide 130 is formed overall and is then an-isotropically etched to form spacers 130 on both of the PMOS and NMOS gate structures. Subsequently, a third patterned masking of photo resist 400 is formed over the PMOS region and to act as the protection layer of PMOS region when NMOS region is subjected to ion implantation. The wafer is then subjected to N type ion implantation 420 to form heavily doped regions 421 of NMOS. Thereafter, the photo resist 400 is removed to perform the fabrication process on PMOS region.
Finally, similar masking and fabrication steps as described in FIG. 1B through FIG. 1C are repeated to form the lightly doped region 431 and heavily doped region 441 on the PMOS region, as shown in FIG. 1D. Totally, five masking steps are used in the fabrication process described above and same type of the gate material, the N type ploy-silicon, is formed on both of the NMOS and PMOS gate structures. The gate material of N type poly-silicon formed on PMOS region acts as a buried channel device that causes the punch-through effect during the operating of the Integrated Circuits. Punch-through effect caused by the buried channel device results in uncontrollable threshold voltage of the MOSFET and directly influences the operating reliability of the Integrated Circuits, thus constrains the further shrinking of channel length of CMOSFET. Much effort has been directed to avoid the formation of buried channel device and to simplify the masking steps to reduce the manufacturing cost and improve the yielding efficiency.